Designers of integrated circuit devices (“chips”), generally application-specific integrated circuits (“ASIC”), may use prototyping as part of the electronic design automation process prior to manufacture of the chip by a foundry. Prototyping is one type of hardware-based functional verification that allows the circuit designer can observe the behavior of the circuit design under conditions approximating its final, manufactured performance. During prototyping, a circuit design, generally written in register transfer language (“RTL”) code, is programmed into one or more programmable logic chips, frequently field-programmable gate arrays (“FPGA”) on a prototyping board. FPGA-based prototypes are a fully functional representation of the circuit design, its circuit board, and its input/output (“I/O”) devices. Also, FPGA prototypes generally run at speeds much closer to the clock speed at which the manufactured chip will run than other types of functional verification, making them much more accurate. The circuit design prototype may also be inserted into another electronic circuit so that the circuit design prototype may be observed and tested in an environment in which the manufactured chip will be used. As such, circuit designers may use FPGA prototyping as a vehicle for software co-development and validation, increasing the speed and accuracy of system developments.
Prototyping of a circuit design using programmable logic chips presents several advantages over other types of functional verification, namely emulation using a plurality of emulation processors. First, prototyping using programmable logic chips generally results in higher performance and speed relative to emulation. Second, such higher-speed circuit design prototypes can sometimes even run in real-time, that is, the prototype may run at the intended clock speed of the manufactured chip, rather than a reduced clock speed. This is not always the case, notably for higher performance circuit designs that have clock speeds higher than the maximum allowed by the programmable logic chips. Third, such circuit design prototypes are generally of lower cost than an emulation system using processors.
Exemplary hardware used in prototyping comprises FPGAs or other types of programmable logic chips, input/output circuitry, and interconnect circuitry connecting the programmable logic chips to each other and to the input-output circuitry. An example of commercial prototyping hardware includes the DN7006K1 OPCIe-8T manufactured by the DINI Group of La Jolla, Calif. The DN7006K10PCIe-8T features six Altera Stratix 3 3SL340 (FF1760) FPGAs, a configuration FPGA, global clock generation hardware, interconnect connecting the FPGAs to each other, input/output devices including an eight lane PCI Express Endpoint, and DDR SODIMM slots for the insertion of RAM.
One problem frequently encountered by circuit designers during prototyping is that a FPGA often has less logical capacity than the circuit design, meaning that the number of logic gates available in the FPGA are insufficient to program in all the logic of the circuit design. This is a well-known problem resulting from the fact that the logic of an ASIC is almost always much denser than the logic of an FPGA. Thus, for all but the simplest ASICs, the current state of FPGA technology does not allow the entirety of the logic of a single ASIC to be prototyped within a single FPGA. This may be overcome by using multiple FPGAs for prototyping, where the logic of the circuit design is partitioned among multiple FPGAs. With multiple FPGAs, interconnect is required between the FPGAs for signal flow from one portion of the circuit design logic on a first FPGA to another portion of the circuit design logic on a second FPGA. This results in a requirement that a large number of signals flow between FPGAs, using many of the FPGA I/O pins. FPGAs have a limited number of pins for power, data, clocks, management, and miscellaneous other required signals. Techniques such as signal multiplexing and partitioning optimization, attempt to minimize the signal flow between FPGAs to minimize the limited number of FPGA I/O pins used.
Current FPGA prototyping designs deal with some of the problems of a limited number of FPGA I/O pins, which also limits the total number of clock lines that can be routed into and out of each FPGA. One partial solution is to use software that efficiently distributes the logic between FPGAs to minimize the number of signals flowing between FPGAs. Another way to deal with the problem is to multiplex signal pins, so that more than one signal may be carried on a single interconnect between I/O pins, freeing up yet more I/O pins for clock signals. Either technique may free up a number of I/O pins for clock lines. However, these techniques still inadequate as the number of FPGA and ASIC logic gates continue to grow in size faster than the number of available I/O pins.
Most modern chip designs have a large number of clocks because circuit designers find the use of multiple clocks to bestow certain performance advantages in their circuit designs. An exemplary clock specification is shown in Table A below. Each clock value is given in units of Megahertz (MHz).
TABLE AclockFrequency -add{ CLK127.00}clockFrequency -add{ CLK227.00}clockFrequency -add{ CLK374.00}clockFrequency -add{ CLK475.00}clockFrequency -add{ CLK5600.00}clockFrequency -add{ CLK6241.00}clockFrequency -add{ CLK7160.00}clockFrequency -add{ CLK833.00}
Each of the clock frequencies listed in Table A are in whole numbers of Megahertz for ease of understanding, but the clock frequencies may be, and often are, non-whole number values. For example CLK5 is indicated as 600.00, but may just as easily be 600.374 MHz. What is more, an ordinary modern circuit design may have dozens of different clocks, whereas this example has eight. In order for prototyping to be most effective, the prototype needs to match as closely as possible the functionality of the circuit design as it will be manufactured, which includes the prototype using the same number of clocks as the circuit design.
Additionally, in an ideal prototyping system, the frequencies would be the same in the prototype as they are in the circuit design prototype. However, present-day FPGAs frequently do not operate at the highest clock frequencies of the circuit design. As a result, lower clock frequencies must be used.
In most FPGA-based prototyping systems, clock signals are generated by a central clock generator that is on the prototyping board, but not part of any FPGA hosting a circuit design partition. These user clock signals are then distributed to each FPGA, often without regard to whether any of the logic of that FPGA used that particular user clock. Using this method of clock generation, there may be many user clock lines occupying a greater number of FPGA I/O pins than is desirable.